----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:45:29 05/26/2010 
-- Design Name: 
-- Module Name:    ADConverter_Interface - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADConverter_Interface is
      Port ( 
			  Reset : in  STD_LOGIC;
			  ADinA : in STD_LOGIC_VECTOR (11 downto 0);
			  ADinB : in STD_LOGIC_VECTOR (11 downto 0);
           ADClkIn : in  STD_LOGIC;
			  ADoutA : out  STD_LOGIC_VECTOR (11 downto 0);
			  ADoutB : out  STD_LOGIC_VECTOR (11 downto 0);
			  NewData : out STD_LOGIC
				);
end ADConverter_Interface;

architecture Behavioral of ADConverter_Interface is

begin


P1:process (ADClkIn,Reset)
variable ClkPos : STD_LOGIC := '0';
begin
	if Reset = '1' then
		ClkPos:='0';
		ADoutA<="000000000000";
		ADoutB<="000000000000";
	else
		--if rising edge
		if ADClkIn='1' and ClkPos='0' then 
			ClkPos:='1';
			-- Channel A
			ADoutA<= ADinA;
			-- Channel B
			ADoutB<= ADinB;
			NewData<='1';
		-- if falling edge
		elsif ClkPos='1' and  ADClkIn='0' then 
			ClkPos:='0';
			NewData<='0';
		end if;
	end if;
end process;

end Behavioral;

